Cadence Allegro Sigrity 16.62
 

Cadence Allegro Sigrity 16.62


Cadence Design Systems, Inc. released an updated version Cadence Sigrity 6.62, with technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance.


Increases in IC speed, faster data transmission rates, smaller geometries, and an emphasis on optimization have made power and signal integrity issues tightly connected. To address these issues, designers need advanced power integrity and power-aware signal integrity tools. This level of technology allows designers to see the complete picture and achieve signoff-level verification through their analysis. Mistakes are not an option on projects this advanced, that's why designers choose proven Sigrity solutions, from Cadence.

By adopting Sigrity solutions, designers can perform three major tasks of the design verification process:

- Analyze the complete power delivery system across chips, packages, and boards.
- Perform system-level signal integrity (SI) analysis, including simultaneous switching noise analysis of high-speed signal transmissions.
- Utilize the advanced physical design tools for single and multi-chip packages, state-of-the-art 3D packages, and systems-in-package (SiPs).

What?s New in 16.62

ASIS 16.62 introduces three new products to the Allegro Sigrity Product Line:

- Allegro Sigrity PI Base
The Allegro Sigrity PI Base is a complement to the Allegro Sigrity SI Base (PA5700) in that it utilizes the Allegro canvas for viewing and casual editing of Allegro PCB, Package, or SiP files. PI Base provides first order Power Integrity checks to be performed. The tool is meant to be used either by designers who need to seek guidance during the layout process, or by Power Integrity experts, who need a quick answer, and understand the confidence level that can be applied with the first-order analysis.
- Allegro Sigrity Signoff and Optimization Option
The Allegro Sigrity Power Integrity Signoff and Optimization Option integrates with PI Base to provide expert-level power integrity analysis on top of an editing canvas that allows for the design to be changed and reanalyzed in an integrated fashion. This Option includes the ability to run all of these Sigrity tools (one at a time) either directly from the PI Base (PA5800) or as a point tool: PowerDC, OptimizePI, PowerSI, 3D-EM, CAD Translators
- IO-SSO Analysis Suite
The IO-SSO Analysis Suite is a specific group of model creation and analysis tools that provides the ability to accurately simulate a group of parallel bus nets that are switching simultaneously. For example, a DDR3 data bus could have as many as 64 simultaneous switching signals. The noise on the power and ground planes, known as simultaneous switching noise (SSN), must be accurately characterized to understand if the data will always be reliable. This suite of tools provides all the functionality required for modeling chip, package, and PCB from die to die. The simulation tool provided understands modern memory interface protocols (such as DDR3/DDR4) and points out violations to the electrical specification for those standard protocols. This Suite includes the ability to run all of these Sigrity tools (one at a time) as a point tool: T2B, XcitePI Extraction, XtractIM, PowerSI, Broadband SPICE, SystemSI ? PBA, CAD Translators



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